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Datasheet File OCR Text:

16-Bit, 250MSPS/200MSPS/130MSPS ADC
ISLA216P
The ISLA216P is a family of low power, high performance 16-bit analog-to-digital converters. Designed with Intersil's proprietary FemtoChargeTM technology on a standard CMOS process, the family supports sampling rates of up to 250MSPS. The ISLA216P is part of a pin-compatible portfolio of 12 to 16-bit A/Ds with maximum sample rates ranging from 130MSPS to 500MSPS. A serial peripheral interface (SPI) port allows for extensive configurability, as well as fine control of various parameters such as gain and offset. Digital output data is presented in selectable LVDS or CMOS formats. The ISLA216P is available in a 72-contact QFN package with an exposed paddle. Operating from a 1.8V supply, performance is specified over the full industrial temperature range (-40C to +85C).
Features
* Single Supply 1.8V Operation * Clock Duty Cycle Stabilizer * 75fs Clock Jitter * 700MHz Bandwidth * Programmable Built-in Test Patterns * Multi-ADC Support * SPI Programmable Fine Gain and Offset Control * Support for Multiple ADC Synchronization * Optimized Output Timing * Nap and Sleep Modes * 200s Sleep Wake-up Time * Data Output Clock * DDR LVDS-Compatible or LVCMOS Outputs * User-accessible Digital Temperature Monitor
Key Specifications
* SNR @ 250/200/130MSPS * 75.0/76.6/77.5dBFS fIN = 30MHz * 72.1/72.6/72.4dBFS fIN = 363MHz * SFDR @ 250/200/130MSPS * 87/91/96dBc fIN = 30MHz * 81/80/82dBc fIN = 363MHz * Total Power Consumption = 786mW @ 250MSPS
Applications
* Radar Array Processing * Software Defined Radios * Broadband Communications * High-Performance Data Acquisition * Communications Test Equipment
CLKDIVRSTN
CLKDIVRSTP
Pin-Compatible Family
OVDD
CLKDIV
AVDD
MODEL ISLA216P25 ISLA216P20
CLKOUTP CLKOUTN
RESOLUTION 16 16 16 14 14 14 14 12 12 12 12
SPEED (MSPS) 250 200 130 500 250 200 130 500 250 200 130
CLKP CLKN
CLOCK MANAGEMENT
ISLA216P13 ISLA214P50 ISLA214P25 ISLA214P20
VINP SHA VINN + -
16-BIT 250 MSPS ADC
D[14:0]P DIGITAL ERROR C R EC N O R TIO D[14:0]N
ISLA214P13 ISLA212P50 ISLA212P25 ISLA212P20 ISLA212P13
VCM
SPI CONTROL
RESETN
NAPSLP
January 13, 2011 FN7574.0
1
RLVDS
OVSS
AVSS
CSB SCLK SDIO SDO
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved Intersil (and design) and FemtoCharge are trademarks owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.
ISLA216P Pin Configuration - LVDS MODE
ISLA216P (72 LD QFN) TOP VIEW
OVDD OVSS OVSS AVDD AVDD AVDD SCLK SDIO SDO DNC DNC CSB D0N D2N D4N 55 54 DNC 53 DNC 52 D6P 51 D6N 50 DNC 49 DNC 48 CLKOUTP 47 CLKOUTN 46 RLVDS 45 OVSS 44 D8P 43 D8N 42 DNC 41 DNC 40 D10P 39 D10N
Thermal Pad Not Drawn to Scale, Consult Mechanical Drawing for Physical Dimensions
D0P
D2P
72 DNC DNC NAPSLP VCM AVSS AVDD AVSS VINN VINN 1 2 3 4 5 6 7 8 9
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
VINP 10 VINP 11 AVSS 12 AVDD 13 AVSS 14 CLKDIV 15 IPTAT 16 DNC 17 Connect Thermal Pad to AVSS RESETN 18 19 AVDD 20 AVDD 21 AVDD 22 CLKP 23 CLKN 24 CLKDIVRSTP 25 CLKDIVRSTN 26 OVSS 27 OVDD 28 DNC 29 DNC 30 D14N 31 D14P 32 OVDD 33 DNC 34 DNC 35 D12N 36 D12P
D4P 56
38 DNC 37 DNC
Pin Descriptions - 72 Ld QFN, LVDS Mode
PIN NUMBER 1, 2, 17, 28, 29, 33, 34, 37, 38, 41, 42, 49, 50, 53, 54, 57, 58 6, 13, 19, 20, 21, 70, 71, 72 5, 7, 12, 14 27, 32, 62 26, 45, 61, 65 3 LVDS PIN NAME DNC Do Not Connect LVDS PIN FUNCTION
AVDD AVSS OVDD OVSS NAPSLP
1.8V Analog Supply Analog Ground 1.8V Output Supply Output Ground Tri-Level Power Control (Nap, Sleep modes)
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FN7574.0 January 13, 2011
ISLA216P Pin Descriptions - 72 Ld QFN, LVDS Mode
PIN NUMBER 4 8, 9 10, 11 15 16 18 22, 23 24, 25 30 31 35 36 39 40 43 44 46 47, 48 51 52 55 56 59 60 63 64 66 67 68 69 Exposed Paddle LVDS PIN NAME VCM VINN VINP CLKDIV IPTAT RESETN CLKP, CLKN CLKDIVRSTP, CLKDIVRSTN D14N D14P D12N D12P D10N D10P D8N D8P RLVDS CLKOUTN, CLKOUTP D6N D6P D4N D4P D2N D2P D0N D0P SDO CSB SCLK SDIO AVSS Common Mode Output Analog Input Negative Analog Input Positive Tri-Level Clock Divider Control Temperature Monitor (Output current proportional to absolute temperature) Power On Reset (Active Low) Clock Input True, Complement Synchronous Clock Divider Reset True, Complement DDR Logical Bits 14, 15 Complement DDR Logical Bits 14, 15 True DDR Logical Bits 12, 13 Complement DDR Logical Bits 12, 13 True DDR Logical Bits 10, 11 Complement DDR Logical Bits 10, 11 True DDR Logical Bits 8, 9 Complement DDR Logical Bits 8, 9 True LVDS Bias Resistor (Connect to OVSS with 1%10k) LVDS Clock Output Complement, True DDR Logical Bits 6, 7 Complement DDR Logical Bits 6, 7 True DDR Logical Bits 4, 5 Complement DDR Logical Bits 4, 5 True DDR Logical Bits 2, 3 Complement DDR Logical Bits 2, 3 True DDR Logical Bits 0, 1 Complement DDR Logical Bits 0, 1 True SPI Serial Data Output SPI Chip Select (active low) SPI Clock SPI Serial Data Input/Output Analog Ground
(Continued)
LVDS PIN FUNCTION
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FN7574.0 January 13, 2011
ISLA216P Pin Configuration - CMOS MODE
ISLA216P (72 LD QFN) TOP VIEW
OVDD AVDD AVDD AVDD OVSS OVSS SDIO SCLK DNC DNC DNC DNC DNC 55 54 DNC 53 DNC 52 D6 51 DNC 50 DNC 49 DNC 48 CLKOUT 47 DNC 46 RLVDS 45 OVSS 44 D8 43 DNC 42 DNC 41 DNC 40 D10 39 DNC
Thermal Pad Not Drawn to Scale, Consult Mechanical Drawing for Physical Dimensions
SDO
CSB
D0
D2
72 DNC DNC NAPSLP VCM AVSS AVDD AVSS VINN VINN 1 2 3 4 5 6 7 8 9
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
VINP 10 VINP 11 AVSS 12 AVDD 13 AVSS 14 CLKDIV 15 IPTAT 16 DNC 17 RESETN 18 19 AVDD 20 AVDD 21 AVDD Connect Thermal Pad to AVSS
D4 56
38 DNC 37 DNC 36 D12
22 CLKP
23 CLKN
24 CLKDIVRSTP
25 CLKDIVRSTN
26 OVSS
27 OVDD
28 DNC
29 DNC
30 DNC
31 D14
32 OVDD
33 DNC
34 DNC
35 DNC
Pin Descriptions - 72 Ld QFN, CMOS Mode
PIN NUMBER 1, 2, 17, 28, 29, 30, 33, 34, 35, 37, 38, 39, 41, 42, 43, 47, 49, 50, 51, 53, 54, 55, 57, 58, 59, 63 6, 13, 19, 20, 21, 70, 71, 72 5, 7, 12, 14 27, 32, 62 26, 45, 61, 65 3 CMOS PIN NAME DNC Do Not Connect CMOS PIN FUNCTION
AVDD AVSS OVDD OVSS NAPSLP
1.8V Analog Supply Analog Ground 1.8V Output Supply Output Ground Tri-Level Power Control (Nap, Sleep modes)
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FN7574.0 January 13, 2011
ISLA216P Pin Descriptions - 72 Ld QFN, CMOS Mode
PIN NUMBER 4 8, 9 10, 11 15 16 18 22, 23 24, 25 31 36 40 44 46 48 52 56 60 64 66 67 68 69 Exposed Paddle CMOS PIN NAME VCM VINN VINP CLKDIV IPTAT RESETN CLKP, CLKN CLKDIVRSTP, CLKDIVRSTN D14 D12 D10 D8 RLVDS CLKOUT D6 D4 D2 D0 SDO CSB SCLK SDIO AVSS Common Mode Output Analog Input Negative Analog Input Positive Tri-Level Clock Divider Control Temperature Monitor (Output current proportional to absolute temperature) Power On Reset (Active Low) Clock Input True, Complement Synchronous Clock Divider Reset True, Complement DDR Logical Bits 14, 15 DDR Logical Bits 12, 13 DDR Logical Bits 10, 11 DDR Logical Bits 8, 9 LVDS Bias Resistor (Connect to OVSS with 1%10k) CMOS Clock Output DDR Logical Bits 6, 7 DDR Logical Bits 4, 5 DDR Logical Bits 2, 3 DDR Logical Bits 0, 1 SPI Serial Data Output SPI Chip Select (active low) SPI Clock SPI Serial Data Input/Output Analog Ground
(Continued)
CMOS PIN FUNCTION
Ordering Information
PART NUMBER (Notes 1, 2) ISLA216P13IRZ ISLA216P20IRZ ISLA216P25IRZ Coming Soon ISLA216P13IR1Z Coming Soon ISLA216P20IR1Z Coming Soon ISLA216P25IR1Z ISLA216P25EVAL NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. For Moisture Sensitivity Level (MSL), please see device information page for ISLA216P. For more information on MSL please see techbrief TB363. PART MARKING ISLA216P13 IRZ ISLA216P20 IRZ ISLA216P25 IRZ ISLA216P13 IR1Z ISLA216P20 IR1Z ISLA216P25 IR1Z Evaluation Board TEMP. RANGE (C) -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C PACKAGE (Pb-free) 72 Ld QFN 72 Ld QFN 72 Ld QFN 48 Ld QFN 48 Ld QFN 48 Ld QFN PKG. DWG. # L72.10x10E L72.10x10E L72.10x10E TBD TBD TBD
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FN7574.0 January 13, 2011
ISLA216P Table of Contents
Pin-Compatible Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - LVDS MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Descriptions - 72 Ld QFN, LVDS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Descriptions - 72 Ld QFN, CMOS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Digital Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Switching Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power-On Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 User Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Temperature Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Nap/Sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Clock Divider Synchronous Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SPI Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SPI Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Device Configuration/Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Global Device Configuration/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Digital Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Equivalent Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 A/D Evaluation Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Split Ground and Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Clock Input Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Exposed Paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Bypass and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 LVDS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 LVCMOS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 30 31 31 32
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FN7574.0 January 13, 2011
ISLA216P
Absolute Maximum Ratings
AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V Analog Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V Clock Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V Logic Inputs to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V Latchup (Tested per JESD-78C;Class 2,Level A) . . . . . . . . . . . . . . . . 100mA
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) 72 Ld QFN (Notes 3, 4) . . . . . . . . . . . . . . . . 23 0.9 48 Ld QFN (Notes 3, 4) . . . . . . . . . . . . . . . . 24 1.0 Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 4. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Boldface limits apply over the operating temperature range, -40C to +85C. ISLA216P25 PARAMETER SYMBOL CONDITIONS
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, TA = -40C to +85C (typical specifications at +25C), AIN = -2dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade).
ISLA216P20 ISLA216P13 MAX (Note 5) UNITS
MIN MAX MIN (Note 5) TYP (Note 5) (Note 5) TYP
MAX MIN (Note 5) (Note 5) TYP
DC SPECIFICATIONS (Note 6) Analog Input
Full-Scale Analog Input Range Input Resistance Input Capacitance Full Scale Range Temp. Drift Input Offset Voltage Common-Mode Output Voltage Common-Mode Input Current (per pin) Clock Inputs Inputs Common Mode Voltage CLKP,CLKN Input Swing 0.9 1.8 0.9 1.8 0.9 1.8 V V VFS RIN CIN AVTC VOS VCM ICM Differential Differential Differential Full Temp -5.0 1.95 2.0 300 9 180 -1.7 0.94 10.8 5.0 -5.0 2.2 1.95 2.0 300 9 180 -1.7 0.94 10.8 5.0 -5.0 2.2 1.95 2.0 300 9 180 -1.7 0.94 10.8 5.0 2.2 VP-P pF ppm/C mV V A/MSPS
Power Requirements
1.8V Analog Supply Voltage 1.8V Digital Supply Voltage 1.8V Analog Supply Current 1.8V Digital Supply Current (Note 6) Power Supply Rejection Ratio AVDD OVDD IAVDD
I OVDD
1.7 1.7
1.8 1.8 372
1.9 1.9 397 73
1.7 1.7
1.8 1.8 342 58 -65
1.9 1.9 360 68
1.7 1.7
1.8 1.8 293 50 -65
1.9 1.9 310 58
V V mA mA dB
3mA LVDS 30MHz, 50mVP-P signal on AVDD
64 -65
PSRR
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FN7574.0 January 13, 2011
ISLA216P
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, TA = -40C to +85C (typical specifications at +25C), AIN = -2dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). Boldface limits apply over the operating temperature range, -40C to +85C. (Continued)
ISLA216P25 PARAMETER SYMBOL CONDITIONS ISLA216P20 ISLA216P13 MAX (Note 5) UNITS
MIN MAX MIN (Note 5) TYP (Note 5) (Note 5) TYP
MAX MIN (Note 5) (Note 5) TYP
Total Power Dissipation
Normal Mode PD 2mA LVDS 3mA LVDS Nap Mode Sleep Mode Nap/Sleep Mode Wakeup Time PD PD CSB at logic high Sample Clock Running 771 786 88 7 200 846 103 19 706 720 83 7 400 770 99 19 603 616 77 7 630 662 94 19 mW mW mW mW s
AC SPECIFICATIONS
Differential Nonlinearity Integral Nonlinearity Minimum Conversion Rate (Note 7) Maximum Conversion Rate Signal-to-Noise Ratio (Note 8) DNL INL fS MIN fS MAX SNR fIN = 30MHz fIN = 105MHz fIN = 190MHz fIN = 363MHz fIN = 461MHz fIN = 605MHz Signal-to-Noise and Distortion (Note 8) SINAD fIN = 30MHz fIN = 105MHz fIN = 190MHz fIN = 363MHz fIN = 461MHz fIN = 605MHz Effective Number of Bits (Note 8) ENOB fIN = 30MHz fIN = 105MHz fIN = 190MHz fIN = 363MHz fIN = 461MHz fIN = 605MHz 70.0 71.7 250 75.0 74.9 74.2 72.1 71.1 69.2 74.7 74.1 73.1 71.6 69.2 65.7 12.12 11.34 12.02 11.85 11.60 11.20 10.62 73.2 74.8 fIN = 30MHz No Missing Codes fIN = 30MHz -0.99 0.35 10 40 200 76.6 76.4 75.3 72.6 71.1 69.2 76.5 76.1 74.7 71.7 68.6 64.9 12.42 11.87 12.35 12.12 11.62 11.10 10.49 72.6 75.5 -0.99 0.25 6 40 130 77.5 76.9 75.3 72.4 70.8 68.9 77.4 76.1 74.6 71.9 67.9 66.3 12.56 11.77 12.35 12.10 11.65 10.99 10.72 -0.99 0.25 5 40 LSB LSB MSPS MSPS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS Bits Bits Bits Bits Bits Bits
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FN7574.0 January 13, 2011
ISLA216P
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, TA = -40C to +85C (typical specifications at +25C), AIN = -2dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). Boldface limits apply over the operating temperature range, -40C to +85C. (Continued)
ISLA216P25 PARAMETER Spurious-Free Dynamic Range (Note 8) SYMBOL SFDR CONDITIONS fIN = 30MHz fIN = 105MHz fIN = 190MHz fIN = 363MHz fIN = 461MHz fIN = 605MHz Spurious-Free Dynamic SFDRX23 fIN = 30MHz Range Excluding H2, H3 fIN = 105MHz (Note 8) fIN = 190MHz fIN = 363MHz fIN = 461MHz fIN = 605MHz Intermodulation Distortion Word Error Rate Full Power Bandwidth NOTES: 5. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 6. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. IOVDD specifications apply for 10pF load on each digital output. 7. The DLL Range setting must be changed for low-speed operation. 8. Minimum specification guaranteed when calibrated at +85C. IMD fIN = 70MHz fIN = 170MHz WER FPBW 74 ISLA216P20 ISLA216P13 MAX (Note 5) UNITS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBFS dBFS
MIN MAX MIN (Note 5) TYP (Note 5) (Note 5) TYP 87 83 81 81 73 67 89 80 92 88 83 82 79 94 87 10-12 700 82 74 91 89 84 80 72 67 91 93 92 87 85 82 92 87 10-12 700
MAX MIN (Note 5) (Note 5) TYP 96 72 83 83 82 70 67 99 82 96 96 94 91 89 88 87 10-12 700
MHz
Digital Specifications
Boldface limits apply over the operating temperature range, -40C to +85C.
SYMBOL CONDITIONS MIN (Note 5) TYP MAX (Note 5) UNITS
PARAMETER
INPUTS
Input Current High (RESETN) Input Current Low (RESETN) Input Current High (SDIO) Input Current Low (SDIO) Input Current High (CSB) Input Current Low (CSB) Input Voltage High (SDIO, RESETN) Input Voltage Low (SDIO, RESETN) Input Current High (CLKDIV) (Note 9) Input Current Low (CLKDIV) Input Capacitance IIH IIL IIH IIL IIH IIL VIH VIL IIH IIL CDI 16 -34 25 -25 3 VIN = 1.8V VIN = 0V VIN = 1.8V VIN = 0V VIN = 1.8V VIN = 0V 1.17 0.63 34 -16 -600 40 0 -25 1 -12 4 -415 58 5 10 -7 12 -300 75 10 A A A A A A V V A A pF
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FN7574.0 January 13, 2011
ISLA216P
Digital Specifications
Boldface limits apply over the operating temperature range, -40C to +85C. (Continued)
SYMBOL CONDITIONS MIN (Note 5) TYP MAX (Note 5) UNITS
PARAMETER
LVDS INPUTS (CLKRSTP,CLKRSTN)
Input Common Mode Range Input Differential Swing (peak to peak, single-ended) CLKDIVRSTP Input Pull-down Resistance CLKDIVRSTN Input Pull-up Resistance VICM VID RIpd RIpu 825 250 100 100 1575 450 mV mV k k
LVDS OUTPUTS
Differential Output Voltage (Note 10) Output Offset Voltage Output Rise Time Output Fall Time VT VOS tR tF 3mA Mode 3mA Mode 1120 612 1150 240 240 1200 mVP-P mV ps ps
CMOS OUTPUTS
Voltage Output High Voltage Output Low Output Rise Time Output Fall Time NOTES: 9. The Tri-Level Inputs internal switching thresholds are approximately. 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending on desired function. 10. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak singled-ended swing is 1/2 of the differential swing. VOH VOL tR tF IOH = -500A IOL = 1mA OVDD - 0.3 OVDD - 0.1 0.1 1.8 1.4 0.3 V V ns ns
Timing Diagrams
INP
INN tA CLKN CLKP tCPD CLKOUTN CLKOUTP tDC D[14/12/.../2/0]N D[14/12/.../2/0]P tPD ODD N-L EVEN N-L ODD N-L+1 EVEN N-L+1 EVEN N-1 ODD N EVEN N LATENCY = L CYCLES
FIGURE 1A. LVDS
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FN7574.0 January 13, 2011
ISLA216P Timing Diagrams
INP
INN tA CLKN CLKP tCPD LATENCY = L CYCLES
CLKOUT tDC tPD D[14/12/.../2/0] ODD N-L EVEN N-L ODD N-L+1 EVEN N-L+1 EVEN N-1 ODD N EVEN N
FIGURE 1B. CMOS FIGURE 1. TIMING DIAGRAMS
Switching Specifications
PARAMETER
Boldface limits apply over the operating temperature range, -40C to +85C.
SYMBOL CONDITION MIN (Note 5) TYP MAX (Note 5) UNITS
ADC OUTPUT
Aperture Delay RMS Aperture Jitter Input Clock to Output Clock Propagation Delay tA jA tCPD tCPD Relative Input Clock to Output Clock Propagation Delay (Note 13) Input Clock to Data Propagation Delay Output Clock to Data Propagation Delay, LVDS Mode Output Clock to Data Propagation Delay, CMOS Mode Synchronous Clock Divider Reset Setup Time (with respect to the positive edge of CLKP) Synchronous Clock Divider Reset Hold Time (with respect to the positive edge of CLKP) Synchronous Clock Divider Reset Recovery Time Latency (Pipeline Delay) dtCPD tPD tDC tDC tRSTS Rising/Falling Edge Rising/Falling Edge AVDD, OVDD = 1.7V to 1.9V, TA = -40C to +85C AVDD, OVDD = 1.8V, TA = +25C AVDD, OVDD = 1.7V to 1.9V, TA = -40C to +85C 1.65 1.9 -450 1.65 -0.1 -0.1 0.4 2.4 0.16 0.2 0.06 114 75 2.4 2.3 3 2.75 450 3.5 0.5 0.65 ps fs ns ns ps ns ns ns ns
tRSTH tRSTRT L DLL recovery time after Synchronous Reset
0.02 52 10
0.35
ns s cycles
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FN7574.0 January 13, 2011
ISLA216P
Switching Specifications
PARAMETER Overvoltage Recovery
Boldface limits apply over the operating temperature range, -40C to +85C. (Continued)
SYMBOL tOVR
t
CONDITION
MIN (Note 5)
TYP 1
MAX (Note 5)
UNITS cycles
SPI INTERFACE (Notes 11, 12)
SCLK Period
CLK
Write Operation Read Operation Read or Write Write Write Read or Write Read
16 16 28 5 6 4 5
cycles cycles cycles cycles cycles cycles cycles
tCLK CSB to SCLK Setup Time CSB after SCLK Hold Time Data Valid to SCLK Setup Time Data Valid after SCLK Hold Time Data Valid after SCLK Time NOTES: tS tH tDS tDH tDVR
11. SPI Interface timing is directly proportional to the ADC sample period (tS). Values above reflect multiples of a 4ns sample period, and must be scaled proportionally for lower sample rates. ADC sample clock must be running for SPI communication. 12. The SPI may operate asynchronously with respect to the ADC sample clock. 13. The relative propagation delay is the difference in propagation time between any two devices that are matched in temperature and voltage, and is specified over the full operating temperature and voltage range.
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25C, AIN = -2dBFS, fIN = 105MHz, fSAMPLE = 250MSPS.
95
HD2 AND HD3 MAGNITURE (dBc)
SNR (dBFS) AND SFDR (dBc)
-65 SFDR @ 130MSPS SFDR @ 250MSPS -70 -75 -80 -85 -90 -95 -100 -105 0 100 HD3 @ 130MSPS HD2 @ 130MSPS 200 300 400 INPUT FREQUENCY (MHz) 500 600 HD3 @ 250MSPS HD2 @ 250MSPS
90 85 80 75 70 65 60 0 100
SNR @ 130MSPS SNR @ 250MSPS
200 300 400 500 INPUT FREQUENCY (MHz)
600
FIGURE 2. SNR AND SFDR vs fIN
100
HD2 AND HD3 MAGNITUDE
FIGURE 3. HD2 AND HD3 vs fIN
-40
90 80
SNR AND SFDR
SFDR(dBfs) SNR(dBfs) SFDR(dBc)
-50 -60 -70 -80 -90 -100 -110 -60 -50 HD3 (dBc)
HD2 (dBc)
70 60 50 40 30 20 10 -60
SNR(dBc)
HD2 (dBfs) HD3 (dBfs)
-50
-40 -30 -20 INPUT AMPLITUDE (dBFS)
-10
0
-40 -30 -20 INPUT AMPLITUDE (dBFS)
-10
0
FIGURE 4. SNR AND SFDR vs AIN
FIGURE 5. HD2 AND HD3 vs AIN
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FN7574.0 January 13, 2011
ISLA216P Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25C, AIN = -2dBFS, fIN = 105MHz, fSAMPLE = 250MSPS. (Continued)
90 SFDR 85 HD2 AND HD3 MAGNITUDE (dBc) SNR (dBFS) AND SFDR (dBc) -75 -80 -85 -90 -95 -100 -105 70 H2 H3
80
75
SNR
70
70
90
110
130
150
170
190
210
230
250
90
110
130
150
170
190
210
230
250
SAMPLE RATE (MSPS)
SAMPLE RATE (MSPS)
FIGURE 6. SNR AND SFDR vs f SAMPLE
FIGURE 7. HD2 AND HD3 vs fSAMPLE
800 750 TOTAL POWER (mW) 700 650 600 550 500 450 40
DNL (LSBs)
1.5 1.0 0.5 0 -0.5 -1.0 -1.5
60
80
100 120 140 160 180 200 220 240 SAMPLE RATE (MSPS)
0
10,000
20,000
30,000 40,000 CODES
50,000
60,000
FIGURE 8. POWER vs fSAMPLE IN 3mA LVDS MODE
FIGURE 9. DIFFERENTIAL NONLINEARITY
20 SNR (dBFS) AND SFDR (dBc) 15 10 INL (LSBs) 5 0 -5 -10 -15 -20 0 10,000 20,000 30,000 40,000 CODES 50,000 60,000
85 SFDR 80
75
SNR
70
65
60 0.75
0.85
0.95
1.05
1.15
INPUT COMMON MODE (V)
FIGURE 10. INTEGRAL NONLINEARITY
FIGURE 11. SNR AND SFDR vs VCM
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FN7574.0 January 13, 2011
ISLA216P Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25C, AIN = -2dBFS, fIN = 105MHz, fSAMPLE = 250MSPS. (Continued)
25000 0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 AIN = -2 dBFS SNR = 75.4 dBFS SFDR = 82 dBc SINAD = 74.5 dBFS
20000 NUMBER OF HITS
15000
10000
5000
0
32696 32700 32704 32708 32712 32716 32720 32724 CODE
0
20
40 60 80 FREQUENCY (MHz)
100
120
FIGURE 12. NOISE HISTOGRAM
FIGURE 13. SINGLE-TONE SPECTRUM @ 105MHz
0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120
AMPLITUDE (dBFS)
AIN = -2 dBFS SNR = 74.5 dBFS SFDR = 81 dBc SINAD = 73.67 dBFS
0 -20 -40 -60 -80 -100 -120 AIN = -2 dBFS SNR = 72.4 dBFS SFDR = 80 dBc SINAD = 71.3 dBFS
0
20
40
60
80
100
120
0
20
40
60
80
100
120
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 14. SINGLE-TONE SPECTRUM @ 190MHz
FIGURE 15. SINGLE-TONE SPECTRUM @ 363MHz
0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 IMD2 IMD3 2nd Harmonics 3rd Harmonics
IMD3 = -94dBFS
0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 IMD2 IMD3 2nd Harmonics 3rd Harmonics IMD3 = -87dBFS
0
20
40
60
80
100
120
0
20
40
60
80
100
120
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 16. TWO-TONE SPECTRUM (F1 = 70MHz, F2 = 71MHz AT -7dBFS)
FIGURE 17. TWO-TONE SPECTRUM (F1 = 170MHz, F2 = 171MHz AT -7dBFS)
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FN7574.0 January 13, 2011
ISLA216P Theory of Operation
Functional Description
The ISLA216P25 is based upon a 16-bit, 250MSPS A/D converter core that utilizes a pipelined successive approximation architecture (Figure 18). The input voltage is captured by a Sample-Hold Amplifier (SHA) and converted to a unit of charge. Proprietary charge-domain techniques are used to successively compare the input to a series of reference charges. Decisions made during the successive approximation operations determine the digital code for each input value. Digital error correction is also applied, resulting in a total latency of 10 clock cycles. This is evident to the user as a latency between the start of a conversion and the data being available on the digital outputs. A user-initiated reset can subsequently be invoked in the event that the above conditions cannot be met at power-up. After the power supply has stabilized the internal POR releases RESETN and an internal pull-up pulls it high, which starts the calibration sequence. If a subsequent user-initiated reset is desired, the RESETN pin should be connected to an open-drain driver with an off-state/high impedance state leakage of less than 0.5mA to assure exit from the reset state so calibration can start. The calibration sequence is initiated on the rising edge of RESETN, as shown in Figure 19. Calibration status can be determined by reading the cal_status bit (LSB) at 0xB6. This bit is `0' during calibration and goes to a logic `1' when calibration is complete. The data outputs produce 0xCCCC during calibration; this can also be used to determine calibration status. While RESETN is low, the output clock (CLKOUTP/CLKOUTN) is set low. Normal operation of the output clock resumes at the next input clock edge (CLKP/CLKN) after RESETN is de-asserted. At 250MSPS the nominal calibration time is 200ms, while the maximum calibration time is 550ms.
Power-On Calibration
As mentioned previously, the cores perform a self-calibration at start-up. An internal power-on-reset (POR) circuit detects the supply voltage ramps and initiates the calibration when the analog and digital supply voltages are above a threshold. The following conditions must be adhered to for the power-on calibration to execute successfully: * A frequency-stable conversion clock must be applied to the CLKP/CLKN pins * DNC pins must not be connected * SDO has an internal pull-up and should not be driven externally * RESETN is pulled low by the ADC internally during POR. External driving of RESETN is optional. * SPI communications must not be attempted
CLOCK GENERATION
INP SHA INN
2.5-BIT FLASH
2.5-BIT FLASH
6- STAGE 1.5-BIT/ STAGE
3- STAGE 1- BIT/ STAGE
3-BIT FLASH
1.25V
+ -
DIGITAL ERROR CORRECTION
LVDS/ LVCMOS OUTPUTS
FIGURE 18. A/D CORE BLOCK DIAGRAM
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FN7574.0 January 13, 2011
ISLA216P
CLKN CLKP CALIBRATION TIME RESETN CAL_STATUS BIT CALIBRATION BEGINS CALIBRATION COMPLETE CLKOUTP
The performance of the ISLA216P25 changes with variations in temperature, supply voltage or sample rate. The extent of these changes may necessitate recalibration, depending on system performance requirements. Best performance will be achieved by recalibrating the A/D under the environmental conditions at which it will operate. A supply voltage variation of <100mV will generally result in an SNR change of <0.5dBFS and SFDR change of <3dBc. In situations where the sample rate is not constant, best results will be obtained if the device is calibrated at the highest sample rate. Reducing the sample rate by less than 80MSPS will typically result in an SNR change of <0.5dBFS and an SFDR change of <3dBc. Figures 20 through 25 show the effect of temperature on SNR and SFDR performance with power on calibration performed at -40C, +25C, and +85C. Each plot shows the variation of SNR/SFDR across temperature after a single power on calibration at -40C, +25C and +85C. Best performance is typically achieved by a user-initiated power on calibration at the operating conditions, as stated earlier. However, it can be seen that performance drift with temperature is not a very strong function of the temperature at which the power on calibration is performed.
FIGURE 19. CALIBRATION TIMING
User Initiated Reset
Recalibration of the A/D can be initiated at any time by driving the RESETN pin low for a minimum of one clock cycle. An open-drain driver with a drive strength in its high impedance state of less than 0.5mA is recommended, as RESETN has an internal high impedance pull-up to OVDD. As is the case during power-on reset, RESETN and DNC pins must be in the proper state for the calibration to successfully execute.
Temperature Calibration
77 76 75 SNR (dBFS) 74 73 72 71 70 -40 -20 0 CAL DONE AT +85 20 40 60 80 CAL DONE AT -40 SFDR (dBc) CAL DONE AT +25 95 90 85 80 75 CAL DONE AT +85 70 65 -40 CAL DONE AT -40 CAL DONE AT +25
-20
0
20
40
60
80
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 20. TYPICAL SNR PERFORMANCE vs TEMPERATURE, 250MSPS OPERATION, fIN=105MHz
78.0 CAL DONE AT -40 77.5 SNR (dBFS)
FIGURE 21. TYPICAL SFDR PERFORMANCE vs TEMPERATURE, 250MSPS OPERATION, fIN=105MHz
100 CAL DONE AT +25 CAL DONE AT -40
95 SFDR (dBc) 90
77.0 76.5 76.0 75.5 -40 CAL DONE AT +85
CAL DONE AT +25
85
CAL DONE AT +85
80 75 -40
-20
0
20
40
60
80
-20
TEMPERATURE (C)
0 20 40 TEMPERATURE (C)
60
80
FIGURE 22. TYPICAL SNR PERFORMANCE vs TEMPERATURE, 200MSPS OPERATION, fIN=105MHz
FIGURE 23. TYPICAL SFDR PERFORMANCE vs TEMPERATURE, 200MSPS OPERATION, fIN=105MHz
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FN7574.0 January 13, 2011
ISLA216P Temperature Calibration (Continued)
80 79 CAL DONE AT -40 SNR (dBFS) SFDR (dBc) 78 77 CAL DONE AT +85 76 75 -40 CAL DONE AT +25 -20 0 20 40 60 80 88 87 86 85 84 83 82 81 80 -40 -20 0 20 40 60 80 CAL DONE AT -40 CAL DONE AT +25 CAL DONE AT +85
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 24. TYPICAL SNR PERFORMANCE vs TEMPERATURE, 130MSPS OPERATION, fIN=105MHz
FIGURE 25. TYPICAL SFDR PERFORMANCE vs TEMPERATURE, 130MSPS OPERATION, fIN=105MHz
Analog Input
A single fully differential input (VINP/VINN) connects to the sample and hold amplifier (SHA) of each unit A/D. The ideal full-scale input voltage is 2.0V, centered at the VCM voltage of 0.94V as shown in Figure 26.
1.8 VINP 1.4 1.0 0.6 0.2 1.0V
1000pF
ADTL1-12
TX-2-5-1
A/D
VCM
1000pF
VINN VCM 0.94V
FIGURE 28. TRANSMISSION-LINE TRANSFORMER INPUT FOR HIGH IF APPLICATIONS
This dual transformer scheme is used to improve common-mode rejection, which keeps the common-mode level of the input matched to VCM. The value of the shunt resistor should be determined based on the desired load impedance. The differential input resistance of the ISLA216P25 is 300. The SHA design uses a switched capacitor input stage (see Figure 42), which creates current spikes when the sampling capacitance is reconnected to the input voltage. This causes a disturbance at the input which must settle before the next sampling point. Lower source impedance will result in faster settling and improved performance. Therefore a 2:1 or 1:1 transformer and low shunt resistance are recommended for optimal performance.
FIGURE 26. ANALOG INPUT RANGE
Best performance is obtained when the analog inputs are driven differentially. The common-mode output voltage, VCM, should be used to properly bias the inputs as shown in Figures 27 through 29. An RF transformer will give the best noise and distortion performance for wideband and/or high intermediate frequency (IF) inputs. Two different transformer input schemes are shown in Figures 27 and 28.
ADT1-1WT ADT1-1WT
1000pF
A/D
A/D
VCM
0.1F
FIGURE 29. DIFFERENTIAL AMPLIFIER INPUT FIGURE 27. TRANSFORMER INPUT FOR GENERAL PURPOSE APPLICATIONS
A differential amplifier, as shown in the simplified block diagram in Figure 29, can be used in applications that require DC-coupling. In this configuration, the amplifier will typically dominate the achievable SNR and distortion performance.
FN7574.0 January 13, 2011
17
ISLA216P
Intersil's new ISL552xx differential amplifier family can also be used in certain AC applications with minimal performance degradation. Contact the factory for more information. sampling instant shown in Figure1A. The internal aperture jitter combines with the input clock jitter in a root-sum-square fashion, since they are not statistically correlated, and this determines the total jitter in the system. The total jitter, combined with other noise sources, then determines the achievable SNR.
Clock Input
The clock input circuit is a differential pair (see Figure 43). Driving these inputs with a high level (up to 1.8VP-P on each input) sine or square wave will provide the lowest jitter performance. A transformer with 4:1 impedance ratio will provide increased drive levels. The clock input is functional with AC-coupled LVDS, LVPECL, and CML drive levels. To maintain the lowest possible aperture jitter, it is recommended to have high slew rate at the zero crossing of the differential clock input signal. The recommended drive circuit is shown in Figure 30. A duty range of 40% to 60% is acceptable. The clock can be driven single-ended, but this will reduce the edge rate and may impact SNR performance. The clock inputs are internally self-biased to AVDD/2 to facilitate AC coupling.
TC4-19G2+ 1000pF CLKP 0.01F 200 CLKN 1000pF
FIGURE 30. RECOMMENDED CLOCK DRIVE
Voltage Reference
A temperature compensated internal voltage reference provides the reference charges used in the successive approximation operations. The full-scale range of each A/D is proportional to the reference voltage. The nominal value of the voltage reference is 1.25V.
Digital Outputs
Output data is available as a parallel bus in LVDS-compatible(default) or CMOS modes. In either case, the data is presented in double data rate (DDR) format. Figures 1A and 1B show the timing relationships for LVDS and CMOS modes, respectively. Additionally, the drive current for LVDS mode can be set to a nominal 3mA(default) or a power-saving 2mA. The lower current setting can be used in designs where the receiver is in close physical proximity to the A/D. The applicability of this setting is dependent upon the PCB layout, therefore the user should experiment to determine if performance degradation is observed. The output mode can be controlled through the SPI port, by writing to address 0x73, see "Serial Peripheral Interface" on page 22. An external resistor creates the bias for the LVDS drivers. A 10k, 1% resistor must be connected from the RLVDS pin to OVSS.
1000pF
Jitter
In a sampled data system, clock jitter directly impacts the achievable SNR performance. The theoretical relationship between clock jitter (tJ) and SNR is shown in Equation 1 and is illustrated in Figure 31.
1 SNR = 20 log 10 ------------------ 2f t IN J
100 95 90 85 SNR (dB) 80 75 70 65 60 55 50 1M tj = 100ps tj = 10ps 10 BITS tj = 1ps tj = 0.1ps 14 BITS
Power Dissipation
The power dissipated by the ISLA216P25 is primarily dependent on the sample rate and the output modes: LVDS vs CMOS and DDR vs SDR. There is a static bias in the analog supply, while the remaining power dissipation is linearly related to the sample rate. The output supply dissipation changes to a lesser degree in LVDS mode, but is more strongly related to the clock frequency in CMOS mode.
(EQ. 1)
Nap/Sleep
Portions of the device may be shut down to save power during times when operation of the A/D is not required. Two power saving modes are available: Nap, and Sleep. Nap mode reduces power dissipation to <103mW while Sleep mode reduces power dissipation to <19mW. All digital outputs (Data, CLKOUT and OR) are placed in a high impedance state during Nap or Sleep. The input clock should remain running and at a fixed frequency during Nap or Sleep, and CSB should be high. Recovery time from Nap mode will increase if the clock is stopped, since the internal DLL can take up to 52s to regain lock at 250MSPS. By default after the device is powered on, the operational state is controlled by the NAPSLP pin as shown in Table 1.
12 BITS
10M 100M INPUT FREQUENCY (Hz)
1G
FIGURE 31. SNR vs CLOCK JITTER
This relationship shows the SNR that would be achieved if clock jitter were the only non-ideal factor. In reality, achievable SNR is limited by internal factors such as linearity, aperture jitter and thermal noise. Internal aperture jitter is the uncertainty in the 18
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TABLE 1. NAPSLP PIN SETTINGS NAPSLP PIN AVSS Float AVDD MODE Normal Sleep Nap
GRAY CODE 15 14 13
Converting back to offset binary from Gray code must be done recursively, using the result of each bit for the next lower bit as shown in Figure 33.
****
1
0
The power-down mode can also be controlled through the SPI port, which overrides the NAPSLP pin setting. Details on this are contained in "Serial Peripheral Interface" on page 22.
Data Format
Output data can be presented in three formats: two's complement(default), Gray code and offset binary. The data format can also be controlled through the SPI port, by writing to address 0x73. Details on this are contained in "Serial Peripheral Interface" on page 22. Offset binary coding maps the most negative input voltage to code 0x000 (all zeros) and the most positive input to 0xFFF (all ones). Two's complement coding simply complements the MSB of the offset binary representation. When calculating Gray code the MSB is unchanged. The remaining bits are computed as the XOR of the current bit position and the next most significant bit. Figure 32 shows this operation.
BINARY 15 14 13
BINARY 15 14 13
****
****
****
1
0
Mapping of the input voltage to the various data formats is shown in Table 2.
TABLE 2. INPUT VOLTAGE TO OUTPUT CODE MAPPING INPUT VOLTAGE OFFSET BINARY 0000 0000 0000 0000 0000 0000 0000 0001 1000 0000 0000 0000 1111 1111 1111 1110 1111 1111 1111 1111 TWO'S COMPLEMENT 1000 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0000 0111 1111 1111 1110 0111 1111 1111 1111 GRAY CODE 0000 0000 0000 0000 0000 0000 0000 0001 1100 0000 0000 0000 1000 0000 0000 0001 1000 0000 0000 0000
****
1
0
****
-Full Scale -Full Scale + 1LSB Mid-Scale +Full Scale - 1LSB +Full Scale
GRAY CODE
15
14
13
****
1
0
FIGURE 32. BINARY TO GRAY CODE CONVERSION
Clock Divider Synchronous Reset
An output clock (CLKOUTP, CLKOUTN) is provided to facilitate latching of the sampled data. This clock is at half the frequency of the sample clock, and the absolute phase of the output clocks for multiple A/Ds is indeterminate. This feature allows the phase of multiple A/Ds to be synchronized (refer to Figure 34), which greatly simplifies data capture in systems employing multiple A/Ds. The reset signal must be well-timed with respect to the sample clock (See "Switching Specifications" on page 11).
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SAMPLE CLOCK INPUT s1 ANALOG INPUT s2
(Note 13)
L+td
tRSTH CLKDIVRSTP (Note 14) tRSTS tRSTRT ADC1 OUTPUT DATA
s0
s1
s2
s3
ADC1 CLKOUTP ADC2 OUTPUT DATA ADC2 CLKOUTP (phase 1) (Note 14) ADC2 CLKOUTP (phase 2) (Note 15)
NOTES:
13. Delay equals fixed pipeline latency (L cycles) plus fixed analog propagation delay td. 14. CLKDIVRSTP setup and hold times are with respect to input sample clock rising edge. CLKDIVRSTN is not shown, but must be driven, and is the compliment of CLKDIVRSTP. 15. Either Output Clock Phase (phase 1 or phase 2 ) equally likely prior to synchronization.
s0
s1
s2
s3
FIGURE 34. SYNCHRONOUS RESET OPERATION
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CSB
SCLK
SDIO
R/W
W1
W0
A12
A11
A10
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
FIGURE 35. MSB-FIRST ADDRESSING
CSB
SCLK
SDIO
A0
A1
A2
A11
A12
W0
W1
R/W
D0
D1
D2
D3
D4
D5
D6
D7
FIGURE 36. LSB-FIRST ADDRESSING
tDSW CSB tS
tDHW
tHI tLO
tCLK
tH
SCLK
SDIO R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0
SPI WRITE
FIGURE 37. SPI WRITE
t DSW CSB tS t DHW
HI
t
t CLK t
LO
t DVR
t
H
SCLK
SDIO R/W SDO W1 W0 A12
WRITING A READ COMMAND A11 A10 A9 A2 A1 A0
READING DATA( 3 WIRE MODE ) D7 D6 D3 D2 D1 D0
( 4 WIRE MODE ) D7 SPI READ D3 D2 D1 D0
FIGURE 38. SPI READ
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CSB CSB STALLING
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD 2
FIGURE 39. 2-BYTE TRANSFER
CSB
LAST LEGAL CSB STALLING
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD N
FIGURE 40. N-BYTE TRANSFER
Serial Peripheral Interface
A serial peripheral interface (SPI) bus is used to facilitate configuration of the device and to optimize performance. The SPI bus consists of chip select (CSB), serial clock (SCLK) serial data output (SDO), and serial data input/output (SDIO). The maximum SCLK rate is equal to the A/D sample rate (fSAMPLE) divided by 16 for both write operations and read operations. At fSAMPLE = 250MHz, maximum SCLK is 15.63MHz for writing and read operations. There is no minimum SCLK rate. The following sections describe various registers that are used to configure the SPI or adjust performance or functional parameters. Many registers in the available address space (0x00 to 0xFF) are not defined in this document. Additionally, within a defined register there may be certain bits or bit combinations that are reserved. Undefined registers and undefined values within defined registers are reserved and should not be selected. Setting any reserved register or value may produce indeterminate results.
concurrently, but only one slave device can be read from at a given time (again, only in three-wire mode). If multiple slave devices are selected for reading at the same time, the results will be indeterminate. The communication protocol begins with an instruction/address phase. The first rising SCLK edge following a high-to-low transition on CSB determines the beginning of the two-byte instruction/address command; SCLK must be static low before the CSB transition. Data can be presented in MSB-first order or LSB-first order. The default is MSB-first, but this can be changed by setting 0x00[6] high. Figures 35 and 36 show the appropriate bit ordering for the MSB-first and LSB-first modes, respectively. In MSB-first mode, the address is incremented for multi-byte transfers, while in LSB-first mode it's decremented. In the default mode, the MSB is R/W, which determines if the data is to be read (active high) or written. The next two bits, W1 and W0, determine the number of data bytes to be read or written (see Table 3). The lower 13 bits contain the first address for the data transfer. This relationship is illustrated in Figure 37, and timing values are given in "Switching Specifications Boldface limits apply over the operating temperature range, -40C to +85C." on page 11. After the instruction/address bytes have been read, the appropriate number of data bytes are written to or read from the A/D (based on the R/W bit status). The data transfer will continue as long as CSB remains low and SCLK is active. Stalling of the CSB pin is allowed at any byte boundary (instruction/address or data) if the number of bytes being transferred is three or less. For transfers of four bytes or more, CSB is allowed to stall in the middle of the instruction/address bytes or before the first data byte. If CSB transitions to a high state after that point the state machine will reset and terminate the data transfer.
SPI Physical Interface
The serial clock pin (SCLK) provides synchronization for the data transfer. By default, all data is presented on the serial data input/output (SDIO) pin in three-wire mode. The state of the SDIO pin is set automatically in the communication protocol (described in the following). A dedicated serial data output pin (SDO) can be activated by setting 0x00[7] high to allow operation in four-wire mode. The SPI port operates in a half duplex master/slave configuration, with the ISLA216P25 functioning as a slave. Multiple slave devices can interface to a single master in three-wire mode only, since the SDO output of an unaddressed device is asserted in four wire mode. The chip-select bar (CSB) pin determines when a slave device is being addressed. Multiple slave devices can be written to
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TABLE 3. BYTE TRANSFER SELECTION [W1:W0] 00 01 10 11 BYTES TRANSFERRED 1 2 3 4 or more
Device Configuration/Control
A common SPI map, which can accommodate single-channel or multi-channel devices, is used for all Intersil A/D products.
ADDRESS 0X20: OFFSET_COARSE_ADC0 ADDRESS 0X21: OFFSET_FINE_ADC0
The input offset of the A/D core can be adjusted in fine and coarse steps. Both adjustments are made via an 8-bit word as detailed in Table 4. The data format is twos complement. The default value of each register will be the result of the self-calibration after initial power-up. If a register is to be incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register.
TABLE 4. OFFSET ADJUSTMENTS PARAMETER Steps -Full Scale (0x00) Mid-Scale (0x80) +Full Scale (0xFF) Nominal Step Size 0x20[7:0] COARSE OFFSET 255 -133LSB (-47mV) 0.0LSB (0.0mV) +133LSB (+47mV) 1.04LSB (0.37mV) 0x21[7:0] FINE OFFSET 255 -5LSB (-1.75mV) 0.0LSB +5LSB (+1.75mV) 0.04LSB (0.014mV)
Figures 39 and 40 illustrate the timing relationships for 2-byte and N-byte transfers, respectively. The operation for a 3-byte transfer can be inferred from these diagrams.
SPI Configuration
ADDRESS 0X00: CHIP_PORT_CONFIG
Bit ordering and SPI reset are controlled by this register. Bit order can be selected as MSB to LSB (MSB first) or LSB to MSB (LSB first) to accommodate various micro controllers. Bit 7 SDO Active Bit 6 LSB First Setting this bit high configures the SPI to interpret serial data as arriving in LSB to MSB order. Bit 5 Soft Reset Setting this bit high resets all SPI registers to default values. Bit 4 Reserved This bit should always be set high. Bits 3:0 These bits should always mirror bits 4:7 to avoid ambiguity in bit ordering.
ADDRESS 0X22: GAIN_COARSE_ADC0 ADDRESS 0X23: GAIN_MEDIUM_ADC0 ADDRESS 0X24: GAIN_FINE_ADC0
Gain of the A/D core can be adjusted in coarse, medium and fine steps. Coarse gain is a 4-bit adjustment while medium and fine are 8-bit. Multiple Coarse Gain Bits can be set for a total adjustment range of 4.2%. (`0011' -4.2% and `1100' +4.2%) It is recommended to use one of the coarse gain settings (-4.2%, -2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and fine-tune the gain using the registers at 0x0023 and 0x24. The default value of each register will be the result of the self-calibration after initial power-up. If a register is to be incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register.
TABLE 5. COARSE GAIN ADJUSTMENT 0x22[3:0] core 0 0x26[3:0] core 1 Bit3 Bit2 Bit1 Bit0 NOMINAL COARSE GAIN ADJUST (%) +2.8 +1.4 -2.8 -1.4
ADDRESS 0X02: BURST_END
If a series of sequential registers are to be set, burst mode can improve throughput by eliminating redundant addressing. In 3-wire SPI mode, the burst is ended by pulling the CSB pin high. If the device is operated in 2-wire mode the CSB pin is not available. In that case, setting the burst_end address determines the end of the transfer. During a write operation, the user must be cautious to transmit the correct number of bytes based on the starting and ending addresses. Bits 7:0 Burst End Address This register value determines the ending address of the burst data.
Device Information
ADDRESS 0X08: CHIP_ID ADDRESS 0X09: CHIP_VERSION
The generic die identifier and a revision number, respectively, can be read from these two registers.
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TABLE 6. MEDIUM AND FINE GAIN ADJUSTMENTS PARAMETER Steps -Full Scale (0x00) Mid-Scale (0x80) +Full Scale (0xFF) Nominal Step Size 0x23[7:0] MEDIUM GAIN 256 -2% 0.00% +2% 0.016% 0x24[7:0] FINE GAIN 256 -0.20% 0.00% +0.2% 0.0016%
Output Data Clock (250MHz) No clock_slip Output Data Clock (250MHz) 1 clock_slip Output Data Clock (250MHz) 2 clock_slip
SPI feature, which allows the rising edge of the output data clock to be advanced by one input clock period, as shown in the Figure 41. Execution of a phase_slip command is accomplished by first writing a '0' to bit 0 at address 0x71, followed by writing a '1' to bit 0 at address 0x71.
ADC Input Clock (500MHz)
2ns 4ns
2ns
ADDRESS 0X25: MODES
Two distinct reduced power modes can be selected. By default, the tri-level NAPSLP pin can select normal operation, nap or sleep modes (refer to"Nap/Sleep" on page 18). This functionality can be overridden and controlled through the SPI. This is an indexed function when controlled from the SPI, but a global function when driven from the pin. This register is not changed by a Soft Reset.
TABLE 7. POWER-DOWN CONTROL VALUE 000 001 010 100 0x25[2:0] POWER DOWN MODE Pin Control Normal Operation Nap Mode Sleep Mode
FIGURE 41. PHASE SLIP
ADDRESS 0X72: CLOCK_DIVIDE
The ISLA216P25 has a selectable clock divider that can be set to divide by two or one (no division). By default, the tri-level CLKDIV pin selects the divisor This functionality can be overridden and controlled through the SPI, as shown in Table 8. This register is not changed by a Soft Reset.
TABLE 8. CLOCK DIVIDER SELECTION VALUE 000 001 010 other 0x72[2:0] CLOCK DIVIDER Pin Control Divide by 1 Divide by 2 Not Allowed
ADDRESS 0X26: OFFSET_COARSE_ADC1 ADDRESS 0X27: OFFSET_FINE_ADC1
The input offset of A/D core#1 can be adjusted in fine and coarse steps in the same way that offset for core#0 can be adjusted. Both adjustments are made via an 8-bit word as detailed in Table 4. The data format is two's complement. The default value of each register will be the result of the self-calibration after initial power-up. If a register is to be incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register.
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output format of the data, as well as the logical coding. The ISLA216P25 can present output data in two physical formats: LVDS(default) or LVCMOS. Additionally, the drive strength in LVDS mode can be set high (default,3mA or low (2mA). Data can be coded in three possible formats: two's complement(default), Gray code or offset binary. See Table 10. This register is not changed by a Soft Reset.
TABLE 9. OUTPUT MODE CONTROL VALUE 000 001 100 0x73[7:5] OUTPUT MODE LVDS 3mA (Default) LVDS 2mA LVCMOS
ADDRESS 0X28: GAIN_COARSE_ADC1 ADDRESS 0X29: GAIN_MEDIUM_ADC1 ADDRESS 0X2A: GAIN_FINE_ADC1
Gain of A/D core #1 can be adjusted in coarse, medium and fine steps in the same way that core #0 can be adjusted. Coarse gain is a 4-bit adjustment while medium and fine are 8-bit. Multiple Coarse Gain Bits can be set for a total adjustment range of 4.2.
Global Device Configuration/Control
ADDRESS 0X71: PHASE_SLIP
The output data clock is generated by dividing down the A/D input sample clock. Some systems with multiple A/Ds can more easily latch the data from each A/D by controlling the phase of the output data clock. This control is accomplished through the use of the phase_slip 24
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TABLE 10. OUTPUT FORMAT CONTROL VALUE 000 010 100 0x73[2:0] OUTPUT FORMAT Two's Complement (Default) Gray Code Offset Binary VALUE 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 UNIT MSPS MSPS TABLE 12. OUTPUT TEST MODES 0xC0[7:4] OUTPUT TEST MODE Off Midscale Positive Full-Scale Negative Full-Scale Reserved Reserved Reserved Reserved User Pattern Reserved Ramp user_patt1 N/A N/A user_patt2 N/A N/A 0x8000 0xFFFF 0x0000 N/A N/A N/A N/A N/A N/A N/A N/A N/A WORD 1 WORD 2
ADDRESS 0X74: OUTPUT_MODE_B ADDRESS 0X75: CONFIG_STATUS
Bit 6 DLL Range This bit sets the DLL operating range to fast (default) or slow. Internal clock signals are generated by a delay-locked loop (DLL), which has a finite operating range. Table 11 shows the allowable sample rate ranges for the slow and fast settings.
TABLE 11. DLL RANGES DLL RANGE Slow Fast MIN 40 80 MAX 100 250
ADDRESS 0XC1: USER_PATT1_LSB ADDRESS 0XC2: USER_PATT1_MSB
These registers define the lower and upper eight bits, respectively, of the user-defined pattern 1.
ADDRESS 0XB6: CALIBRATION STATUS
The LSB at address 0xB6 can be read to determine calibration status. The bit is `0' during calibration and goes to a logic `1' when calibration is complete.This register is unique in that it can be read after POR at calibration, unlike the other registers on chip, which can't be read until calibration is complete.
ADDRESS 0XC3: USER_PATT2_LSB ADDRESS 0XC4: USER_PATT2_MSB
These registers define the lower and upper eight bits, respectively, of the user-defined pattern 2
DEVICE TEST
The ISLA216P25 can produce preset or user defined patterns on the digital outputs to facilitate in-situ testing. A user can pick from preset built-in patterns by writing to the output test mode field [7:4] at 0xC0 or user defined patterns by writing to the user test mode field [2:0] at 0xC0. The user defined patterns should be loaded at address space 0xC1 through 0xD0, see the "SPI Memory Map" on page 27 for more detail.The predefined patterns are shown in Table 12. The test mode is enabled asynchronously to the sample clock, therefore several sample clock cycles may elapse before the data is present on the output bus.
ADDRESS 0XC5: USER_PATT3_LSB ADDRESS 0XC6: USER_PATT3_MSB
These registers define the lower and upper eight bits, respectively, of the user-defined pattern 3
ADDRESS 0XC7: USER_PATT4_LSB ADDRESS 0XC8: USER_PATT4_MSB
These registers define the lower and upper eight bits, respectively, of the user-defined pattern 4.
ADDRESS 0XC9: USER_PATT5_LSB ADDRESS 0XCA: USER_PATT5_MSB
These registers define the lower and upper eight bits, respectively, of the user-defined pattern 5.
ADDRESS 0XC0: TEST_IO
Bits 7:4 Output Test Mode These bits set the test mode according to Table 12. Other values are reserved.User test patterns loaded at 0xC1 through 0xD0 are also available by writing `1000' to [7:4] at 0xC0 and a pattern depth value to [2:0] at 0xC0. See "SPI Memory Map" on page 27. Bits 2:0 User Test Mode The three LSBs in this register determine the test pattern in combination with registers 0xC1 through 0xD0. Refer to the "SPI Memory Map" on page 27.
ADDRESS 0XCB: USER_PATT6_LSB ADDRESS 0XCC: USER_PATT6_MSB
These registers define the lower and upper eight bits, respectively, of the user-defined pattern 6
ADDRESS 0XCD: USER_PATT7_LSB ADDRESS 0XCE: USER_PATT7_MSB
These registers define the lower and upper eight bits, respectively, of the user-defined pattern 7.
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ADDRESS 0XCF: USER_PATT8_LSB ADDRESS 0XD0: USER_PATT8_MSB
These registers define the lower and upper eight bits, respectively, of the user-defined pattern 8. clock rate and divide ratio. A `101' updates the temp counter every ~ 66s (for 250MSPS). Faster updates rates result in lower precision. Bit [0] Select sampler bit. Set to `0'. This set of registers provides digital access to an PTAT or IPTAT-based temperature sensor, allowing the system to estimate the temperature of the die, allowing easy access to information that can be used to decide when to recalibrate the A/D as needed. The nominal transfer function of the temperature counter is Codes (in decimal) = 0.56*T(C) + 618. This corresponds to approximately a 65 LSB increase from -40 to +85C. A typical temperature measurement can occur as follows: 1. Write `0xCA' to address 0x4D - enable temp counter, divide='101' 2. Wait 132s (at 250Msps) - longer wait time ensures the sensor completes one valid cycle. 3. Write `0x20' to address 0x4D - power down, disable temp counter-recommended between measurements. This ensures that the output does not change between MSB and LSB reads. 4. Read address 0x4B (MSBs) 5. Read address 0x4C (LSBs) 6. Record temp code value 7. Write `0x20' to address 0x4D - power-down, disable temp counter. Contact the factory for more information if needed.
Digital Temperature Sensor
ADDRESS 0X4B: TEMP_COUNTER_HIGH
Bits [2:0] of this register hold the 3 MSBs of the 11-bit temperature code. Bit [7] of this register indicates a valid temperature_counter read was performed. A logic `1' indicates a valid read.
ADDRESS 0X4C: TEMP_COUNTER_LOW
Bits [7:0] of this register hold the lower 8 LSBs of the 11-bit temperature code.
ADDRESS 0X4D: TEMP_COUNTER_CONTROL
Bit [7] Measurement mode select bit, set to `1' for recommended PTAT mode. `0' (default) is IPTAT mode and is less accurate and not recommended. Bit [6] Temperature counter enable bit. Set to `1' to enable. Bit [5] Temperature counter power down bit. Set to `1' to power-down temperature counter. Bit [4] Temperature counter reset bit. Set to `1' to reset count. Bit [3:1] Three bit frequency divider field. Sets temperature counter update rate. Update rate is proportional to ADC sample
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ISLA216P SPI Memory Map
ADDR. (Hex) SPI Config/Control 00 01 02 03-07 08 09 0A-0F 10-1F 20 21 22 23 24 25 PARAMETER NAME port_config Reserved burst_end Reserved chip_id chip_version Reserved Reserved offset_coarse_adc0 offset_fine_adc0 gain_coarse_adc0 gain_medium_adc0 gain_fine_adc0 modes_adc0 Reserved Reserved Medium Gain Fine Gain Power Down Mode ADC0 [2:0] 000 = Pin Control 001 = Normal Operation 010 = Nap 100 = Sleep Other codes = Reserved Coarse Offset Fine Offset Reserved Medium Gain Fine Gain Reserved Power Down Mode ADC1 [2:0] 000 = Pin Control 001 = Normal Operation 010 = Nap 100 = Sleep Other codes = Reserved Reserved Reserved Temp Counter [10:8] Temp Counter [7:0] Enable PD Reset Reserved Differential Skew Reserved Next Clock Edge Clock Divide [2:0] 000 = Pin Control 001 = divide by 1 010 = divide by 2 100 = divide by 4 Other codes = Reserved 80h 00h 00h NOT reset by Soft Reset Divider [2:0] Select Read only Read only 00h Coarse Gain BIT 7 (MSB) SDO Active BIT 6 LSB First BIT 5 Soft Reset Reserved Burst end address [7:0] Reserved Chip ID # Chip Version # Reserved Reserved Coarse Offset Fine Offset Coarse Gain cal. value cal. value cal. value cal. value cal. value 00h NOT reset by Soft Reset Read only Read only 00h BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) DEF. VALUE (HEX) 00h Mirror (bit5) Mirror (bit6) Mirror (bit7)
DUT Info
26 27 28 Device Config/Control 29 2A 2B
offset_coarse_adc1 offset_fine_adc1 gain_coarse_adc1 gain_medium_adc1 gain_fine_adc1 modes_adc1
cal. value cal. value cal. value cal. value cal. value 00h NOT reset by Soft Reset
2C-2F 33-4A 4B 4C 4D 4E-6F 70 71 72
Reserved Reserved temp_counter_high temp_counter_low temp_counter_control Reserved skew_diff phase_slip clock_divide
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ISLA216P SPI Memory Map (Continued)
ADDR. (Hex) 73 Device Config/Control PARAMETER NAME output_mode_A BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) DEF. VALUE (HEX) 00h NOT reset by Soft Reset Output Mode [7:5] 000 = LVDS 3mA (Default) 001 = LVDS 2mA 100 = LVCMOS Other codes = Reserved DLL Range 0 = Fast 1 = Slow Default='0' Reserved
Calibration Done
Output Format [2:0] 000 = Two's Complement (Default) 010 = Gray Code 100 = Offset Binary Other codes = Reserved
74
output_mode_B
00h NOT reset by Soft Reset
75-B5 B6 B7-BF C0
Reserved cal_status Reserved test_io Output Test Mode [7:4] 0 = Off (Note 14) 1 = Midscale Short 2 = +FS Short 3 = -FS Short 4 = Reserved (Note15) 5-6 = Reserved 7 = Reserved (Note16) 8 = User Pattern (1 to 4 deep) 9 = Reserved 10 = Ramp 11-15 = Reserved
Read Only
User Test Mode [2:0] 0 = user pattern 1 only 1 = cycle pattern 1,3 2 = cycle pattern 1,3,5 3 = cycle pattern 1,3,5,7 4-7 = NA
00h
C1 C2 Device Test C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1-FF NOTES:
user_patt1_lsb user_patt1_msb user_patt2_lsb user_patt2_msb user_patt3_lsb user_patt3_msb user_patt4_lsb user_patt4_msb user_patt5_lsb user_patt5_msb user_patt6_lsb user_patt6_msb user_patt7_lsb user_patt7_msb user_patt8_lsb user_patt8_msb Reserved
B7 B15 B7 B15 B7 B15 B7 B15 B7 B15 B7 B15 B7 B15 B7 B15
B6 B14 B6 B14 B6 B14 B6 B14 B6 B14 B6 B14 B6 B14 B6 B14
B5 B13 B5 B13 B5 B13 B5 B13 B5 B13 B5 B13 B5 B13 B5 B13
B4 B12 B4 B12 B4 B12 B4 B12 B4 B12 B4 B12 B4 B12 B4 B12 Reserved
B3 B11 B3 B11 B3 B11 B3 B11 B3 B11 B3 B11 B3 B11 B3 B11
B2 B10 B2 B10 B2 B10 B2 B10 B2 B10 B2 B10 B2 B10 B2 B10
B1 B9 B1 B9 B1 B9 B1 B9 B1 B9 B1 B9 B1 B9 B1 B9
B0 B8 B0 B8 B0 B8 B0 B8 B0 B8 B0 B8 B0 B8 B0 B8
0x00 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
14. During Calibration xCCCC (MSB justified) is presented at the output data bus, toggling on the LSB (and higher) data bits occurs at completion of calibration. This behavior can be used as an option to determine calibration state. 15. Use test_io = 0x80 and User Pattern 1 = 0x9999 for Checkerboard outputs on DDR Outputs. 16. Use test_io = 0x80 and User Pattern 1 = 0xAAAA for all ones/zeroes outputs on DDR Outputs.
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FN7574.0 January 13, 2011
ISLA216P Equivalent Circuits
AVDD
AVDD
TO CLOCK-PHASE GENERATION AVDD 11k
AVDD INP
CLKP
CSAMP 9pF TO CHARGE PIPELINE E3
18k
300 AVDD INN
E1
E2 CSAMP 9pF
TO CHARGE PIPELINE E3
AVDD
11k
18k
E1
E2
CLKN
FIGURE 42. ANALOG INPUTS
AVDD AVDD 75k AVDD 75k 280 INPUT 75k 75k TO SENSE LOGIC
INPUT
FIGURE 43. CLOCK INPUTS
AVDD
(20k PULL-UP ON RESETN ONLY) OVDD 20k TO 280 LOGIC OVDD
OVDD
FIGURE 44. TRI-LEVEL DIGITAL INPUTS
OVDD 2mA OR 3mA OVDD DATA DATA D[14:0]P OVDD
DATA
FIGURE 45. DIGITAL INPUTS
OVDD OVDD
D[14:0]
D[14:0]N
DATA
DATA
2mA OR 3mA
FIGURE 46. LVDS OUTPUTS
FIGURE 47. CMOS OUTPUTS
29
FN7574.0 January 13, 2011
ISLA216P Equivalent Circuits (Continued)
AVDD
VCM 0.94V + -
FIGURE 48. VCM_OUT OUTPUT
A/D Evaluation Platform
Intersil offers an A/D Evaluation platform which can be used to evaluate any of Intersil's high speed A/D products. The platform consists of a FPGA based data capture motherboard and a family of A/D daughtercards. This USB based platform allows a user to quickly evaluate the A/D's performance at a user's specific application frequency requirements. More information is available at http://www.intersil.com/converters/adc_eval_platform/
LVDS Outputs
Output traces and connections must be designed for 50 (100 differential) characteristic impedance. Keep traces direct and minimize bends where possible. Avoid crossing ground and power-plane breaks with signal traces.
LVCMOS Outputs
Output traces and connections must be designed for 50 characteristic impedance.
Layout Considerations
Split Ground and Power Planes
Data converters operating at high sampling frequencies require extra care in PC board layout. Many complex board designs benefit from isolating the analog and digital sections. Analog supply and ground planes should be laid out under signal and clock inputs. Locate the digital planes under outputs and logic pins. Grounds should be joined under the chip.
Unused Inputs
Standard logic inputs (RESETN, CSB, SCLK, SDIO, SDO) which will not be operated do not require connection to ensure optimal A/D performance. These inputs can be left floating if they are not used. Tri-level inputs (NAPSLP) accept a floating input as a valid state, and therefore should be biased according to the desired functionality.
Definitions
Analog Input Bandwidth is the analog input frequency at which the spectral output power at the fundamental frequency (as determined by FFT analysis) is reduced by 3dB from its full-scale low-frequency value. This is also referred to as Full Power Bandwidth. Aperture Delay or Sampling Delay is the time required after the rise of the clock input for the sampling switch to open, at which time the signal is held for conversion. Aperture Jitter is the RMS variation in aperture delay for a set of samples. Clock Duty Cycle is the ratio of the time the clock wave is at logic high to the total time of one clock period. Differential Non-Linearity (DNL) is the deviation of any code width from an ideal 1 LSB step.
Clock Input Considerations
Use matched transmission lines to the transformer inputs for the analog input and clock signals. Locate transformers and terminations as close to the chip as possible.
Exposed Paddle
The exposed paddle must be electrically connected to analog ground (AVSS) and should be connected to a large copper plane using numerous vias for optimal thermal performance.
Bypass and Filtering
Bulk capacitors should have low equivalent series resistance. Tantalum is a good choice. For best performance, keep ceramic bypass capacitors very close to device pins. Longer traces will increase inductance, resulting in diminished dynamic performance and accuracy. Make sure that connections to ground are direct and low impedance. Avoid forming ground loops.
30
FN7574.0 January 13, 2011
ISLA216P
Effective Number of Bits (ENOB) is an alternate method of specifying Signal to Noise-and-Distortion Ratio (SINAD). In dB, it is calculated as: ENOB = (SINAD - 1.76)/6.02 Gain Error is the ratio of the difference between the voltages that cause the lowest and highest code transitions to the full-scale voltage less than 2 LSB. It is typically expressed in percent. I2E The Intersil Interleave Engine. This highly configurable circuitry performs estimates of offset, gain, and sample time skew mismatches between the core converters, and updates analog adjustments for each to minimize interleave spurs. Integral Non-Linearity (INL) is the maximum deviation of the A/D's transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of LSBs. Least Significant Bit (LSB) is the bit that has the smallest value or weight in a digital word. Its value in terms of input voltage is VFS/(2N-1) where N is the resolution in bits. Missing Codes are output codes that are skipped and will never appear at the A/D output. These codes cannot be reached with any input value. Most Significant Bit (MSB) is the bit that has the largest value or weight. Pipeline Delay is the number of clock cycles between the initiation of a conversion and the appearance at the output pins of the data. Power Supply Rejection Ratio (PSRR) is the ratio of the observed magnitude of a spur in the A/D FFT, caused by an AC signal superimposed on the power supply voltage. Signal to Noise-and-Distortion (SINAD) is the ratio of the RMS signal amplitude to the RMS sum of all other spectral components below one half the clock frequency, including harmonics but excluding DC. Signal-to-Noise Ratio (without Harmonics) is the ratio of the RMS signal amplitude to the RMS sum of all other spectral components below one-half the sampling frequency, excluding harmonics and DC. SNR and SINAD are either given in units of dB when the power of the fundamental is used as the reference, or dBFS (dB to full scale) when the converter's full-scale input power is used as the reference. Spurious-Free-Dynamic Range (SFDR) is the ratio of the RMS signal amplitude to the RMS value of the largest spurious spectral component. The largest spurious spectral component may or may not be a harmonic.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev.
DATE 1/13/11 REVISION FN7574.0 Initial Release CHANGE
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISLA216P To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff FITs are available from our website at: http://rel.intersil.com/reports/sear
For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com
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FN7574.0 January 13, 2011
ISLA216P
Package Outline Drawing
L72.10x10E
72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 11/09
10.00 9.75 72 1 6 PIN 1 INDEX AREA 9.75 3.000 REF. 6.000 REF. 10.00 A B EXPOSED PAD AREA X Y (3.00 ) (6.00) DETAIL "X" 72 1 6 PIN #1 INDEX AREA Z
8.500 REF. (4X)
0.100 M C A B (4X) 0.15 4.150 REF. TOP VIEW 7.150 REF. BOTTOM VIEW 0.100 M C A B
11 ALL AROUND
9.75 0.10
C0.400X45 (4X) 10.00 0.10 SIDE VIEW (7.15) (4.15 REF)
25 .1 (0 LL A A O R D N )
(0.350)
R0.200 0.450
C0.190X45
1 72
0.500 0.100 R0.115 TYP.
(4X 9.70) (4X 8.50)
DETAIL "Z"
( 72X 0 .23)
R0.200 MAX. ALL AROUND ( 72X 0 .70) 0.100 C 0.650 0.050 0.85 0.050
TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. 2. 3. 4. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to ANSI Y14.5m-1994. Unless otherwise specified, tolerance : Decimal 0.10 Angular 2.50 Dimension applies to the metallized terminal and is measured between 0.015mm and 0.30mm from the terminal tip. 5. 6. Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature. 7. Package outline compliant to JESD-M0220. 0.190~0.245 0.23 0.050 0.50 0.080 C
SEATING PLANE C
0.025 0.020
0.100 M C A B 0.050 M C DETAIL "Y"
32
FN7574.0 January 13, 2011
(1.500)
U

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